1. Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to the liquid crystal display device being adaptable for multi-scanning operation and being able to display image data without adding a complicated circuit thereto and deteriorating image qualities inputted thereto.
2. Description of the Related Art
So-called flat display panels are generally used for image displaying devices of late years. While many kinds of flat display panels having various operating principles thereof have been developed, liquid crystal display devices are mostly used for image display devices of computer terminals or the like above all.
In an active-matrix type liquid crystal display device having an active element like a thin film transistor in each of pixels thereof and switching the active element thereby, a liquid crystal driving voltage (a gray scale voltage) is applied to each pixel electrode thereof via each active element, so that cross talks between the pixels can be avoided. Therefore, the active-matrix type liquid crystal display device enables multiple-gray shade display thereby without applying such a special driving method thereto that is applied to a simple matrix type (or, a passive matrix type) liquid crystal display device for preventing cross talks from appearing in the simple-matrix type liquid crystal display device.
FIG. 18 is a block diagram for explaining an exemplified structure of the active matrix type liquid crystal display devices. FIG. 19 is a timing diagram for explaining various signal waveforms being supplied to a side of the liquid crystal display device shown in FIG. 18 along a horizontal direction thereof, and FIG. 20 is a timing diagram for explaining various signal waveforms being supplied to another side thereof along a vertical direction thereof, respectively related to a display control thereof.
The liquid crystal display device comprises an interface board on which an interface circuit is mounted. Receiving various control signals including display data (pixel data) and clock signals being supplied from an external circuit (like a main frame of a computer) to the liquid crystal display device TFT-LCD, the interface circuit applies the pixel data, the clock signals (also denoted simply as xe2x80x9cclocksxe2x80x9d, hereinafter), and the other various driving voltages to certain portions of the liquid crystal display device.
The interface circuit has a display control device and a power source circuit therein. The display control device outputs and transmits pixel signals to a first pixel of the liquid crystal display device via data bus DB1, the other pixel signals to a second pixel thereof via the other data bus DB2, clocks D1, D2 to drain drivers being mounted thereon for acquiring the pixel signals into the drain drivers respectively, and a frame starting indication signal FSD and a gate clocks (clock G) to gate drivers being mounted thereon for driving the gate driver, respectively. On the other hand, the power source circuit is constituted by a positive voltage generation circuit PVG, a negative voltage generation circuit NVG, a multiplexer MUX for synthesizing the positive voltage and the negative voltage therein, a counter electrode voltage generation circuit CVG for determining the counter electrode potential, and a gate voltage generation circuit GVG.
A liquid crystal display panel TFT-LCD which constitutes this liquid crystal display device has 1024 pixels juxtaposed along a horizontal direction thereof and 768pixels juxtaposed along a vertical direction thereof. The liquid crystal display panel of this sort belongs to so-called XGA-class being defined by pixel number of 1024xc3x97768 thereof. In the interface board for receiving the display data and the control signals sent from the main frame of the computer, red data (R), green data (G), and blue data (B) being received thereat arc divided into groups of two in their respective colors in accordance with every pair of the pixels. For instance, when a red datum, a green datum, and a blue datum corresponding to a first pixel and those corresponding to a second pixel are inputted to the display control device on the interface board as thick arrows in FIG. 18 show, these data arc grouped into a pair of the red data, a pair of the green data, and a pair of the blue data, and then transmitted to the liquid crystal display panel TFT-LCD through respective data buses DB1, DB2 provided for the first and second pixels within a certain period.
The clock signals (also denoted simply as xe2x80x9cClocksxe2x80x9d, hereinafter) defining the aforementioned certain period and having half frequencies as those for respective pixels are sent from the main frame of-the computer through a clock line shown by a thin arrow of FIG. 18. Concretely, the frequency of the clock becomes 32.5 MHz as a half of 65 MHz.
In a construction of the liquid crystal display panel TFT-LCD, a displaying screen thereof is established as a standard thereof, and drain drivers (TFT-drivers) are disposed in a horizontal direction thereof and connected to drain lines of thin film transistors TFT for supplying voltages for driving liquid crystals to the respective thin film transistors. On the other hand, gate drivers are connected to gate lines thereof so as to supply voltages to respective gates of the thin film transistors TFT during a certain period (one horizontal operation time).
The display control device being constituted by semiconductor integrated circuit (e.g. Large Scale Integrated circuit; LSI) receives display data and control signals sent from the main frame of the computer, and outputs various signals for the two pixels in accordance with the display data and the control signals into the data drivers and the gate drivers. Moreover, the data line for every pixel transmits signal of 18 bits (6 bits for each color of R, G, and B).
A two pixels transmission scheme for transmitting display data for every 2 pixels from the main frame of the computer to the display control device and from the display control device to the drain drivers of the liquid crystal display panel is employed, because the display data cannot be transmitted between the aforementioned apparatuses or the apparatus and the drain drivers by a frequency of 65 MHz as a reference clock for every pixel.
As FIGS. 19 and 20 shows, a pulse for one horizontal sweeping period based on a horizontal synchronizing signal and a display timing signal is supplied to the gate drivers for every horizontal sweeping (horizontal scanning) so as to apply a voltage to a gate of the thin film transistor TFT. A frame starting indication signal based on a vertical synchronizing signal is also supplied to the gate drivers so as to start to display an image at a first line of the liquid crystal display panel TFT-LCD (a group of pixels juxtaposed in a horizontal direction at an end of a screen thereof) for every one frame period.A signal waveform as Clock (from External) in FIG. 19 shows a waveform of the aforementioned clock signal inputted from an external circuit (e.g. a main frame of a computer) to the liquid crystal display device thereto.
The positive voltage generation circuit, the negative voltage generation circuit, and the multiplexer being provided in the power source circuit invert directions of electric fields applied to certain liquid crystals for every certain period direction so as to prevent an electric field having a certain direction from being applied to the certain liquid crystals continuously for a long time (Alternation of the liquid crystal driving voltage). The alternation of the liquid crystal driving voltage in this explanation is performed by changing voltages supplied to the drain drivers at either a positive side or a negative side of a counter electrode voltage as a reference for every predetermined period. In this explanation, the alternation is performed in accordance with every frame period. Timings for reversing a polarity of the liquid crystal driving voltage arc controlled by a alternation timing signal ATS supplied from the display control device to the power source circuit.
In the thin film transistor type liquid crystal display device of the aforementioned conventional technology, pixel data acquisitions of the drain drivers (latch-operations of the drain drivers in accordance with the pixel data) have to be finished within one line sweeping period (one line time), and all of the lines have to be operated within the one frame period. Therefore, when a number of the pixel data being inputted to the liquid crystal display device is smaller than that of display pixels thereof and either the one line sweeping period or the one frame period thereof are apparently insufficient for those required for displaying the inputted pixel-number in response to the predetermined clock frequency, the display control device operates erroneously and the control signals cannot be generated properly.
FIG. 21 is an explanatory diagram showing an example of doubly displaying, state appearing on a screen of the conventional liquid crystal display device. If the control signal cannot be generated as mentioned above, pixel data being inputted into a normally operating region of the liquid crystal display device are displayed in other region thereof where the liquid crystals are not driven and the other region which is short of display signals being inputted to the region in a horizontal direction thereof or in a vertical direction thereof. In FIG. 21, in contrast to the displaying area DA in which the display data inputted thereto are normally displayed (as exemplified by an arrangement of letters for every pixel), a black displaying area BAH in accordance with a horizontal retrace period, and a black displaying area BAV in accordance with a vertical retrace period, foreparts of the displaying contents being displayed in the displaying area DA are also displayed in areas denoted as DAHD (Doubly displaying area in a horizontal direction) and DAVD (Doubly displaying areas in a vertical direction), respectively. Such a state that at least a part of the display contents is reproduced and displayed in parallel with each other in a screen of the liquid crystal display panel is called xe2x80x9cDoubly displaying statexe2x80x9d, and affects a displaying screen thereof.
An objective of the present invention is to solve the aforementioned problems and to provide a method for driving a liquid crystal display device suitable to complete each pixel operation and to provide clear images, even if displaying periods of the display data inputted by simple circuitry are insufficient.
For achieving the aforementioned objectives, the present invention utilizes a faster clock signal than that inputted to the liquid crystal display device from an external circuit thereto (e.g., the main frame of the computer) to complete respective operations of the drain drivers being disposed in a horizontal direction (a lateral direction) of the liquid crystal display panel in a short time (e.g. one line time). An oscillator based on a phase-locked loop (PLL) is used for generating the faster clock signals. However, if the faster clock signals are excessively fast, processing at the drain driver will be finished before the displaying periods is up. Therefore, it is preferable for a method for driving a liquid crystal display device according to the present invention to determine whether a clock signal to be outputted from the display control device should be locked in a state as the clock signal is inputted thereto (keeping the clock frequency as that of the inputted state), or changed faster than the inputted state (multiplying the clock frequency higher than that of the inputted state), in accordance with the situations of displaying data period, the vertical retrace period, or else.
As for driving the gate drivers being disposed in a vertical direction (a longitudinal direction) of the liquid crystal display panel, all of lines juxtaposed longitudinally therein have to be scanned (driven) within the one frame time. This operation can be realized by scanning a plurality of the lines simultaneously during the one line. For this operation, a number of the lines being driven simultaneously should be determined in accordance with the displaying datum period or a condition of the vertical retrace period.
The representative configurations of a method for driving a liquid crystal display device structures according to the present invention will be described as follows.
Configuration 1: In a liquid crystal display device comprising a liquid crystal display panel having a plurality of pixels arranged in a matrix manner each of which has an active matrix clement, a plurality of drain drivers for applying voltages based on a plurality of display data corresponding to a group of the plurality of the pixels arranged in a lateral direction of the matrix respectively to the group of the pixels, and a plurality of gate drivers for applying a scanning voltage to each of another group of the plurality of the pixels arranged in a longitudinal direction of the matrix,
the liquid crystal display device further comprises an interface board on which an interface circuit for generating displaying voltages to be applied to the plurality of the drain drivers and the plurality of the gate drivers in accordance with the plurality of the display data and a control signal supplied from an external circuit to the liquid crystal display device (e.g. a main frame of a computer) is mounted,
the interface circuit includes a counter for counting a number N of pixels of the display data being inputted from the external circuit during one horizontal period, a lateral pixel number generating circuit for generating a number (a capacity, or a quota) M of pixels arranged in a lateral direction of the liquid crystal display panel which defines a number of the image data acceptable in the lateral direction, a subtracting circuit for subtracting the number M from the number N (calculating a difference of the (Nxe2x88x92M)), a pixels-number conversion circuit for converting the number N of pixels of the display data to that of the number M (in the case of M greater than N), and a clock frequency multiplying circuit for multiplying a frequency CL of the clock signal supplied from the external circuit by a number of A (A is a natural number equal to or greater than 2).
The number N of the pixel data (included in the image data, mentioned above) arc converted to the number M thereof (M greater than N) using the clock signal of the frequency multiplied A-times by the clock frequency multiplying circuit using the liquid crystal display device constituted as mentioned above, by employing one of following methods (1)-(3).
Method (1): The pixel data are transferred together with the clock signal having a frequency of Axc3x97CL obtained by multiplying the frequency CL by the number A to the drain drivers if the M/N is divisible and provides the A as a quotient of the division.
Method (2): The pixel data are transferred together with the clock signal having the frequency CL (as inputted from the external circuit) to the drain drivers, while the clock signal having a frequency of Axc3x97CL obtained by multiplying the frequency CL by the number A to the drain drivers for scanning the rest (Mxe2x88x92N) pixels (to which the pixel data are not transferred) of the liquid crystal display panel, if the M/N is indivisible.
Method (3): Data for displaying a plain region (e.g. a black displaying region) to are transferred together with the clock signal having a frequency of Axc3x97CL obtained by multiplying the frequency CL by the number A to the drain drivers, if the M/N is indivisible and a product of the N being multiplied by the A is smaller than M (i.e. Axc3x97N less than M).
According to this configuration, multiple scanning processing can be performed by the liquid crystal display panel without the doubly displaying in a horizontal direction thereof.
Configuration 2: In the liquid crystal display device having the configuration 1, wherein a number of pixel lines (each of which is constituted of a group of pixels juxtaposed in the lateral direction of the liquid crystal display panel) arranged in a longitudinal direction of the liquid crystal display panel is M0, a number of pixel lines of the display data being inputted to the interface circuit is N0, and the number M0 is greater than the number N0 (i.e., M0 greater than N0), the liquid crystal display device is driven by one of following methods (4)-(6).
Method (4): A0 rows (A0 is a natural number equal to or greater than 2) of the pixel lines in the liquid crystal display panel from the first line to the A0-th line thereof are scanned simultaneously during one line time, and next A0 rows of the pixel lines from the (A0+1)-th line to the 2A0-th line thereof are scanned simultaneously during in next one line time (after the one line time), if the M0/N0 is divisible and provides the A0 as a quotient of the division.
Method (5): The display data are scanned by every row of the pixel lines during a display period (a scanning period), and data for displaying a plain region (i.e. a black displaying region) are scanned by B lines simultaneously in the vertical retrace period so as to finish scanning (M0xe2x88x92N0) rows of the pixel lines of the liquid crystal display panel within the vertical retrace period, if the M0/N0 is indivisible and provides the number B as a remainder of the division.
Method (6): The display data are scanned by every C rows (C is a natural number equal to or greater than 2) of the pixel lines during a display period (a scanning period), and data for displaying a plain region (i.e. a black displaying region) are scanned by B lines simultaneously in the vertical retrace period so as to finish scanning (M0xe2x88x92N0) rows of the pixel lines of the liquid crystal display panel within the vertical retrace period, if the M0/N0 is indivisible and a product of the number N multiplied by the number C is less than the number M (i.e., Cxc3x97N less than M).
According to this configuration, multiple scanning processing can be performed without doubly displaying in either a horizontal direction or a vertical direction of the liquid crystal display panel.
As a circuit for generating fast clock signals can be constituted on a basis of a phase-locked loop (PLL) without either special technique, a plurality of lines of the liquid crystal display panel can be driven synchronously (simultaneously) by simply combining the circuit with a special-purpose driver thereof without any other circuitry. Moreover, resolution will be determined easily by obtaining the resolution of the display data inputted to the liquid crystal display device using the display timing signals.
Incidentally, the present invention is not limited to any of the above-described structures, and it goes without saying that various modifications can be made without deviating from the technical ideas of the present invention.
These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.